Tapeout is the point where a chip design is finished and its final layout database (GDSII or OASIS) is sent to the foundry to make photomasks. The name comes from the magnetic tape once used to ship the data. Before tapeout the team signs off functional verification, timing, power, physical verification (DRC and LVS), DFT and every open ECO, and freezes the database.
- Tapeout is a sign-off event: every check below should have a dated, stored result.
- DRC and LVS must be clean against the foundry runset version the PDK specifies.
- Every late ECO needs equivalence checking and a fresh timing run before release.
- The GDSII transfer itself can be an export: check classification before it is sent.
What is tapeout in semiconductor design?
Tapeout is the hand-off from design to manufacturing: the point at which the final, signed-off layout database is released to the foundry so that photomasks can be made. The name comes from the era when that data was shipped on magnetic tape: "The name originates from the use of magnetic tape to send the data to the manufacturing facility" (Wikipedia summary). Today the data goes over a secure file transfer, usually as GDSII or OASIS.
The design team treats tapeout as a gate. Once the database is released, a fix means a new mask set or at least new metal masks, so teams hold a formal review where each sign-off owner confirms their check is clean or waived with a reason.
Is it tapeout or tape-out?
Both spellings are used for the same event, and so is "tape out" as a verb ("we tape out in March"). The noun is usually written tapeout or tape-out. A full-mask tapeout makes masks for one design; a multi-project wafer (MPW) or shuttle tapeout shares a mask set among several designs to cut cost, which is common for test chips and start-ups.
Tapeout checklist: the sign-offs before GDSII goes to the foundry
Download the tapeout checklist (CSV); it opens in Excel or Google Sheets with one row per check and columns for owner, evidence, status and date. The checks:
| Area | Check | Evidence to keep |
|---|---|---|
| Functional verification | All regressions pass on the final RTL; functional and code coverage goals met or waived | Regression report, coverage report, waiver list with approvers |
| Formal and equivalence | Logic equivalence RTL to netlist and netlist to final netlist after every ECO | Equivalence reports with no unresolved non-equivalent points |
| CDC and RDC | Clock and reset domain crossing checks clean; waivers reviewed | CDC report and waiver file |
| Static timing | Timing met in all modes and corners, with signoff extraction | STA reports per mode and corner, constraint file version |
| Power integrity | IR drop and electromigration within limits | IR and EM reports |
| Physical verification | DRC, LVS, antenna and density clean on the foundry runset version | DRC and LVS summaries with runset version, waived violations agreed with the foundry |
| DFT | Scan inserted and verified; ATPG coverage at target; memory BIST in place | ATPG coverage report, DFT sign-off |
| IP integration | Every hard IP block at its approved version with its integration checklist | IP version list and vendor sign-off items |
| IO and package | Pad ring, bump map and package netlist agree | IO and package review record |
| ECO closure | Every ECO listed, implemented, re-verified and closed | ECO list with status and verification for each |
| Database | Final GDSII or OASIS with layer map, fill and seal ring; checksums recorded | Release tag, file checksums, foundry submission form |
| Export check | Classification confirmed before the database leaves the country | Classification note from export compliance |
The PDK sets the rules the physical checks run against: in the export rules' words, it is "a software tool provided by a semiconductor manufacturer to ensure that the required design practices and rules are taken into account" (15 CFR part 774). Record which PDK and runset version each sign-off used.
What happens after tapeout?
The foundry then runs its own checks on the database and prepares the mask data, and questions come back as a list the team must answer quickly. Mask making and wafer processing follow, then packaging and bring-up in the lab.
If silicon shows a bug, many teams fix it with a metal-only ECO, which changes only some metal masks and reuses the base layers. That is why spare cells are placed before tapeout and why every ECO after tapeout is recorded as carefully as the original release.
Tapeout checklist example: a small test chip (illustrative)
An illustrative example, not a real company record: a 2 mm by 2 mm test chip on a shuttle run, five days before the database deadline.
| Check | Status | Note |
|---|---|---|
| Regressions | Clean | 1,842 tests pass on tag rtl_v1.4; 3 coverage holes waived by the verification lead |
| Equivalence after ECO-07 | Clean | Run after the late fix to the reset synchronizer |
| STA | Clean | All corners met; one false path added and reviewed |
| DRC | Waived 2 | Two density violations near the seal ring; foundry agreed in writing |
| LVS | Clean | Runset version recorded on the sign-off sheet |
| Export check | Done | Compliance confirmed classification before upload |
| Database | Released | Checksums stored with the release tag; foundry form submitted |
Common tapeout mistakes
Most tapeout problems are record problems: the check was run, but nobody can show which version it ran on.
- Signing off DRC on an old runset after the foundry issued a new PDK version.
- Making a late ECO and skipping equivalence checking or the timing rerun.
- Leaving waivers without an owner or reason, so nobody can tell later why they were accepted.
- Not tagging the exact RTL, netlist and database that went out, so silicon results cannot be traced to a version.
- Forgetting that sending the database abroad is an export that needs a classification check.
Which tapeout records should a team keep?
Keep the sign-off sheet with every report it cites, the release tags, the ECO list and the foundry correspondence, for every tapeout including shuttle runs. Linked to the bug tracker and to silicon bring-up results, they show what was checked, what was waived and what failed in the lab.
Two export rules apply to the files themselves. An export includes "the sending or taking of an item out of the United States, in any manner", and releasing technology to a foreign person in the United States "is a deemed export" (15 CFR 734.13).
Tapeout records as a data asset
Years of sign-off sheets, ECO lists and bring-up results linked to the RTL and bugs behind them are a complete record of how designs were made correct.
AI developers building chip design and verification tools ask for this kind of linked history from the firms that own it. Where a license is agreed, customer designs, foundry PDK content and third-party IP are removed first, and the export classification is checked before anything leaves the company.
If your company keeps years of design and verification records, the guide for chip and electronics design firms explains what AI developers ask for and who signs. To see what yours could be worth, describe them in six questions; no files or system access needed.
Common questions
What does tapeout mean in semiconductor design?
It is the point where the finished layout database of a chip is sent to the foundry to make photomasks. After tapeout, changes need new masks.
Why is it called tapeout?
Design data was once shipped to the mask shop on magnetic tape. The name stayed after the transfer moved to file uploads.
What file format is sent at tapeout?
Usually GDSII or OASIS, with a layer map and the foundry's submission form. The foundry checks the database before mask making.
What checks must pass before a chip tapes out?
Functional verification and coverage, equivalence checks, CDC, static timing in all corners, IR and EM, DRC and LVS on the right runset, DFT and closure of every ECO. Each needs a stored report.
What is the difference between a full-mask and a shuttle tapeout?
A full-mask tapeout makes a mask set for one design. A shuttle or multi-project wafer run shares masks among several designs, which costs less and suits test chips.
What is a metal-only ECO after tapeout?
A fix that changes only some metal layers, using spare cells placed before tapeout, so the base masks can be reused. It is recorded and verified like the original release.
Is sending GDSII to a foundry abroad an export?
Yes. Under 15 CFR 734.13 an export includes sending an item out of the United States in any manner. Check the classification with your export compliance lead first.
How long should tapeout sign-off records be kept?
At least for the life of the product and any customer support obligation; many teams keep them indefinitely because silicon issues years later need the exact version history.
What is Tiny Tapeout?
Tiny Tapeout runs shuttles that, in its own words, make it "more accessible than ever to get your designs manufactured on a real chip". For its TT04 to TT10 chips, the standard tile was about 160 by 100 micrometres, which its FAQ says is enough for about 1,000 digital logic gates, built on the open-source SkyWater 130 nm PDK; extra tiles can be bought for more room.
Sources and further reading
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