UVM, the Universal Verification Methodology, is the IEEE 1800.2 standard class library and method for building reusable SystemVerilog testbenches. Accellera describes it as a standard to enable development and reuse of verification environments and verification IP throughout the electronics industry, and publishes the reference library code.
Why it matters when licensing company data
A UVM testbench is a hierarchy of components: a test, an environment, agents with a sequencer, driver and monitor for each interface, scoreboards and coverage collectors. Transactions and sequences flow through that hierarchy, and phases order how components are built, connected and run. The standard is developed by Accellera's UVM Working Group, and the IEEE notes that it improves interoperability and reduces the cost of rewriting verification IP for each new project or tool.
The 2020 edition of IEEE 1800.2 superseded the 2017 edition. Because UVM components follow one structure, a firm's verification IP for a bus protocol can be reused across many customer projects, which is why design-services firms often treat their UVM libraries as their own core asset, separate from the customer designs they verify.
See the UVM testbench example and the design verification plan template.
Example
A design firm builds UVM agents for AXI and SPI once and reuses them on every customer project, swapping only the configuration and sequences. When it later reviews its records, it treats those agents, their commit history and the bugs they found as its own verification IP, while the customer RTL and the project-specific tests written under each services contract stay with the customers who own them.
Source
IEEE 1800.2-2020, Standard for Universal Verification Methodology. Definition reviewed November 9, 2026 by Origin Data Partners.