# Chip Design Data for AI: What Design Firms Can License

> For ASIC, FPGA, PCB and verification firms: the chip design data AI developers ask for, what you own vs customers and foundries, export rules and a checklist.

Canonical: https://origindatapartners.com/guides/chip-design-firm-data
By: Origin Data Partners
Status: Published
Published: 2026-11-13
Updated: 2026-11-13
Sources checked: 2026-11-13

## Quick answer

Chip design data that AI developers ask for is a firm's own verification history: testbenches, coverage, regression results, bug and ECO records linked to the RTL they tested. A design-services firm can usually offer only what it owns. Customer designs, foundry PDKs, standard-cell libraries and third-party IP stay out, and export classification comes first. No closed price for a design database has been published.

## Key points

- Frontier labs and environment builders are hiring for RTL, verification and physical design work, so demand is real.
- A services firm owns its methods, scripts, verification IP and its own products' history, not its customers' chips.
- Files that embed a foundry PDK, standard cells or licensed IP usually cannot leave the company.
- EAR classification (3E001, 3E991 or EAR99) and deemed-export checks come before any sample.

## Who this page is for

Founders and engineering leads at ASIC and FPGA design-services firms, verification consultancies, PCB design houses and fabless start-ups, including ones that are winding down. It helps most when the firm has several years of projects in version control, a bug tracker and a regression system.

General semiconductor licensing, including process and yield data, is covered in [licensing semiconductor process and design data](https://origindatapartners.com/guides/license-semiconductor-process-data-ai); board files are covered in [Gerber and PCB design data](https://origindatapartners.com/guides/altium-kicad-pcb-design-data-ai). This page is the sector landing for design firms: what buyers ask for, the evidence, who owns what and who signs.


## What chip design data do AI developers ask for?

The demand is for work that shows how a design was made correct, not only the final RTL. Anthropic's chip design team will "Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization" ([Anthropic job post](https://job-boards.greenhouse.io/anthropic/jobs/5459098008)), and OpenAI's AI for Chip Design team will "Build RL environments and evaluations for tasks such as RTL generation, design verification, and physical design optimization" ([OpenAI job post](https://openai.com/careers/research-engineer-ai-for-chip-design-san-francisco/)).

| Record | What it shows | Why the links matter |
| --- | --- | --- |
| RTL with version history | How blocks were written and changed | Each change can be tied to the bug or spec change behind it |
| Testbenches and verification IP | How the design was exercised: sequences, checkers, scoreboards | The method, not only the result; see [UVM testbench example](https://origindatapartners.com/guides/uvm-testbench-example) |
| Verification plans and coverage databases | What had to be proven and how far coverage got | Shows what "done" meant; see [design verification plan template](https://origindatapartners.com/guides/design-verification-plan-template) |
| Regression results and bug tracker history | Which tests failed, the root cause and the fix | A bug linked to its failing test and its RTL fix is a complete worked problem |
| Timing, ECO and sign-off records | Constraints, timing reports, ECO lists, waivers | How the design closed; see [tapeout checklist](https://origindatapartners.com/guides/tapeout-checklist) |
| PCB schematics and layouts with revisions | Board design decisions and changes | See [PCB design data](https://origindatapartners.com/guides/altium-kicad-pcb-design-data-ai) |

Public benchmarks are built from open repositories. Phoenix-bench used "511 verified Verilator instances from 114 GitHub repositories" and found agents struggle "from SWE-bench Verified to Phoenix-bench because hardware bugs propagate across parallel instantiated modules" ([Phoenix-bench](https://arxiv.org/abs/2605.15226)). Private, linked verification history from real projects is what such public sets lack.


## What is chip design data worth to AI developers?

No closed price for a design firm's design or verification database has been published with a source. The evidence is demand, a labour rate and an analyst statement about task prices.

| Evidence | What it says | Grade |
| --- | --- | --- |
| Anthropic, chip design RL | Builds RL environments for RTL, verification and physical design; asks for people who "Have taped out chips" ([Anthropic](https://job-boards.greenhouse.io/anthropic/jobs/5459098008)) | Company claim (job post) |
| OpenAI, AI for Chip Design | Same task list; notes that "To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements" ([OpenAI](https://openai.com/careers/research-engineer-ai-for-chip-design-san-francisco/)) | Company claim (job post) |
| Prime Intellect and Phinity Labs | Open roles: "Applied Researcher - Chip Design" ([Prime Intellect](https://jobs.ashbyhq.com/PrimeIntellect/9ed2340b-029e-4f58-82f5-0d55f09aad5b)) and "Research Engineer - Hardware, Data" ([Phinity Labs](https://jobs.ashbyhq.com/Phinitylabs/510b00e6-c8d3-42ae-8c28-81e91672aef8)) | Company claim (job post titles) |
| Mercor, chip design expert | "Mercor is working with a frontier AI lab on chip design tasks used to train and evaluate AI models", paying "$100 per hour" to review tasks "such as designing or fixing an RTL block or writing a testbench" ([Mercor](https://work.mercor.com/jobs/list_AAABoc1YpFIYUktJmyxFc5mB/chip-design-expert-rtl-design-verification)) | Company claim (listing); a labour rate, not a data price |
| SemiAnalysis GDPx | Built its benchmark with RL environment startups and "wanted chip design to be slightly overrepresented"; says "labs are willing to pay $5k+ for a single high quality task" ([GDPx](https://newsletter.semianalysis.com/p/gdpx-measuring-frontier-model-capabilities)) | Independent analyst statement; no deal cited |

These figures are ceilings and signals, not offers and not prices for a design archive. An hourly rate pays an engineer to write or review a task; a per-task figure pays for a finished, graded problem. A design firm's own history can feed both, which is why the ownership check below matters more than any number.


## Who owns the files in a design-services firm?

Holding a file is not owning it. In a services firm most of the repository was written for customers, and much of what the tools produced embeds someone else's technology. The table is the usual position; your services agreements, foundry agreements and IP licenses decide the real one.

| What is in the repository | Usual owner | Can the firm offer it? |
| --- | --- | --- |
| Your own verification IP, testbench libraries, scripts and flows | The firm | Usually yes, if no customer agreement assigns them |
| Your own products' RTL, bugs and regressions (fabless start-ups) | The firm | Usually yes, after export classification |
| Internal methodology, training material, review checklists | The firm | Usually yes |
| Customer RTL, netlists and layouts built under a services contract | The customer, under most services contracts | Not without the customer's written consent |
| Foundry PDKs and standard-cell libraries | The foundry or library vendor | No; files that embed them stay out |
| Third-party IP cores (processors, SerDes, memory compilers) | The IP vendor | No; their license terms govern |
| EDA tool outputs (timing reports, databases) | Depends on the tool license | Check the license; strip tool-generated libraries |

A PDK is defined in the export rules as "a software tool provided by a semiconductor manufacturer to ensure that the required design practices and rules are taken into account" ([15 CFR part 774](https://www.ecfr.gov/current/title-15/subtitle-B/chapter-VII/subchapter-C/part-774/appendix-Supplement%20No.%201%20to%20Part%20774)). Open PDKs are the exception that shows the rule: "The SkyWater Open Source PDK is released under the Apache 2.0 license" ([SkyWater PDK](https://github.com/google/skywater-pdk)), and so is GlobalFoundries' GF180MCU PDK ([GF180MCU](https://github.com/google/gf180mcu-pdk)). Origin's working assumption, to be checked against your own agreements, is that commercial PDKs, standard-cell libraries and licensed IP come under confidentiality terms (NDAs or license clauses) that forbid disclosure, so any file that embeds them stays out.

Who signs: for the firm's own material, the founder, CEO or board. For a customer design, the customer. In a wind-down the board, an assignee for the benefit of creditors or a bankruptcy trustee acts for the company; see [hardware start-up shutdowns and the CAD archive](https://origindatapartners.com/guides/hardware-company-closing-cad-archive) and [selling data in a 363 sale](https://origindatapartners.com/guides/sell-debtor-data-363-sale).


## Is chip design data export controlled? EAR, 3E001 and deemed exports

This page is general information, not legal advice: it quotes each rule with its source, and your export compliance lead or counsel decides how it applies to your files. A lawyer is needed before any customer design, any file with third-party content or any controlled technology is shared.

Most chip design technology is subject to the Export Administration Regulations (EAR). A "dual-use" item "is one that has civil applications as well as terrorism and military or weapons of mass destruction (WMD)-related applications" ([15 CFR 730.3](https://www.law.cornell.edu/cfr/text/15/730.3)). Category 3 of the Commerce Control List controls design technology: ECCN 3E001 covers "Technology" according to the General Technology Note for the "development" or "production" of commodities controlled by 3A, 3B or 3C (with listed exceptions), 3E905 covers technology for integrated circuits using gate all-around field-effect transistor (GAAFET) structures, and 3E991 covers technology for electronic components "controlled by 3A991" ([15 CFR part 774](https://www.ecfr.gov/current/title-15/subtitle-B/chapter-VII/subchapter-C/part-774/appendix-Supplement%20No.%201%20to%20Part%20774)). A note says "3E001 and 3E905 do not apply to 'Process Design Kits' ('PDKs') unless they include libraries implementing functions or technologies for items specified by 3A001" ([15 CFR part 774](https://www.ecfr.gov/current/title-15/subtitle-B/chapter-VII/subchapter-C/part-774/appendix-Supplement%20No.%201%20to%20Part%20774)).

Items not on the list are "EAR99" ([15 CFR 734.3](https://www.law.cornell.edu/cfr/text/15/734.3)). Even EAR99 data can need a license for embargoed destinations and listed parties. An export includes "the sending or taking of an item out of the United States, in any manner", and "Any release in the United States of "technology" or source code to a foreign person is a deemed export" ([15 CFR 734.13](https://www.law.cornell.edu/cfr/text/15/734.13)). That reaches a buyer's or labelling vendor's staff who are foreign nationals. Since October 2022, BIS has also amended the EAR "to implement necessary controls on advanced computing integrated circuits (ICs), computer commodities that contain such ICs, and certain semiconductor manufacturing items" ([Federal Register](https://www.federalregister.gov/documents/2022/10/13/2022-21658/implementation-of-additional-export-controls-certain-advanced-computing-and-semiconductor-manufacturing)), so advanced-node and AI-accelerator work needs a careful classification.

The [ITAR and EAR checklist](https://origindatapartners.com/guides/itar-ear-checklist-cad-data-ai) walks through classification, CCATS requests and deemed exports step by step; [semiconductor process and design data](https://origindatapartners.com/guides/license-semiconductor-process-data-ai) covers the EAR and NDA questions for chip companies in general.


## Records checklist for a chip or electronics design firm

Write these down before a first conversation; the [sector records checklist (CSV)](https://origindatapartners.com/downloads/sector-records-checklist.csv) holds the same kind of rows for every sector.

| Item | What to write down |
| --- | --- |
| Version control | Git, Perforce or SVN; years of history; whether history survived migrations |
| Bug tracker and regressions | Jira, Bugzilla or an in-house tool; regression system and how long results are kept |
| Coverage | Where coverage databases and verification plans live, per project |
| Projects | Tapeouts or board releases by year, and which were your own products |
| Ownership | For each project: own product, customer-owned, or mixed; data clauses in each services agreement |
| Third-party content | Foundry, PDK and node; standard-cell libraries; licensed IP cores; EDA tool license terms |
| Export classification | ECCN or EAR99 by project; any work for defense customers; who has had access |


## What a one-page datasheet looks like (fictional example)

Invented to show the level of detail; it describes no real company.

| Field | Fictional example |
| --- | --- |
| Company | Verification consultancy, 45 engineers, plus one in-house networking ASIC product |
| Years | Git history 2014 to 2026; bug tracker 2016 to 2026 |
| Own material | UVM verification IP for four bus protocols, regression scripts, the in-house ASIC: RTL, testbench, 2,300 closed bugs linked to fixing commits |
| Excluded | All customer projects; foundry PDK and standard-cell views; licensed SerDes and memory IP |
| Export | In-house ASIC classified EAR99 by counsel; access limited to US persons pending review |
| Signer | CEO, after counsel reviews services agreements and the classification |


## What happens next: three steps

A first conversation needs no files. You can stop after any step.

- Describe your records: [answer six questions](https://origindatapartners.com/check-fit?sector=chips), with no files and no system access. Origin then separates your own material from customer, foundry and IP-vendor content and asks for the export classification of each project.
- Datasheet and sample: Origin turns your answers into a one-page datasheet like the example above, and you approve a small de-identified sample before anything leaves the company.
- Buyers and license: Origin shows the datasheet to the AI developers and data programs that have asked for chip design and verification data, with their published terms. You approve scope, use, price and delivery, and sign the license yourself.
- Origin does not charge data owners; a buyer may pay Origin when a deal closes ([how Origin is paid](https://origindatapartners.com/referral-disclosure)).


## Related sector guides

Firms in this sector often hold records that buyers in neighbouring sectors also ask about: [manufacturer CAD and quality records for AI](https://origindatapartners.com/guides/engineered-product-manufacturer-data); [biotech, CRO and lab assay data for AI](https://origindatapartners.com/guides/biotech-cro-lab-data).

A completed example from a design and process archive: [the semiconductor company case study](https://origindatapartners.com/case-studies/semiconductor-company-data-license-2-4-million).

For firms with about 50 or more staff, buyers pay most for the [whole linked record set across systems](https://origindatapartners.com/guides/sell-linked-company-records-specialty-firm): email, chat, tickets and documents joined to the sector records.


## Running AI agents on your design or verification flow?

Runs of agents that triage regressions or debug failing tests are a separate record set, with their own provider-terms questions. See [licensing agent traces from production](https://origindatapartners.com/guides/license-ai-agent-traces).


## Resources for design and verification engineers

Guides for the people who keep these records, and the detailed pages behind this hub:

- [Tapeout: what it means and a tapeout checklist](https://origindatapartners.com/guides/tapeout-checklist)
- [UVM testbench: architecture and a worked example](https://origindatapartners.com/guides/uvm-testbench-example)
- [Design verification plan template and coverage](https://origindatapartners.com/guides/design-verification-plan-template)
- [Semiconductor process and design data](https://origindatapartners.com/guides/license-semiconductor-process-data-ai)
- [ITAR and EAR checklist before sharing engineering files](https://origindatapartners.com/guides/itar-ear-checklist-cad-data-ai)
- [Gerber and PCB design data](https://origindatapartners.com/guides/altium-kicad-pcb-design-data-ai)
- [Hardware start-up shutdown: the CAD archive](https://origindatapartners.com/guides/hardware-company-closing-cad-archive)

Hold years of design and verification records? [Describe them in six questions, no files needed, and see what your data is worth](https://origindatapartners.com/check-fit?sector=chips).

Origin Data Partners works with companies that own data and helps get it bought. We are independent of the services on this page, and a buyer may pay us when a deal closes ([how Origin is paid](https://origindatapartners.com/referral-disclosure)). [See what your data is worth](https://origindatapartners.com/check-fit).


## Questions and answers

### Can a chip design services firm license its design data to AI companies?

Only the part it owns. Its own verification IP, testbench libraries, scripts, methodology and its own products' history are usually its own. Customer designs need the customer's written consent, and files that embed foundry PDKs, standard cells or licensed IP stay out.

### Who owns RTL written for a customer under a services contract?

Usually the customer, because design services agreements commonly assign the deliverables to the customer. Read the IP and confidentiality clauses of each agreement; they decide, not where the files sit.

### Can files containing a foundry PDK or standard-cell library be shared with an AI developer?

Treat them as out of scope. Commercial PDKs and cell libraries come under the foundry's or vendor's terms, which in Origin's view usually forbid disclosure; check your own agreements. Open PDKs such as SkyWater's are released under Apache 2.0 and are the exception.

### Is RTL and verification data export controlled under the EAR?

It can be. ECCN 3E001 covers technology for developing or producing items controlled under 3A, 3B or 3C, with exceptions, and 3E991 covers technology for 3A991 items; data that is not listed is EAR99. Your export compliance lead or counsel classifies each project before any sample leaves.

### Does a deemed export apply if the AI developer's staff are foreign nationals?

Yes. Under 15 CFR 734.13, releasing technology or source code to a foreign person in the United States is a deemed export to that person's country. Agree in writing who at the buyer and its vendors may open the files.

### What chip design data is most useful to AI developers?

Linked verification history: a bug, the failing test that found it, the RTL fix and the regression that proved it, plus the plan and coverage that defined done. Final RTL alone is less useful.

### What has an AI company paid for a chip design database?

No closed price has been published. The public figures are a $100 per hour rate Mercor lists for experts who review chip tasks, and a SemiAnalysis statement, with no deal cited, that labs are willing to pay $5,000 or more for a single high-quality task. Neither is a price for an archive, and neither is an offer.

### Who signs for a fabless start-up that is shutting down?

The board while the company operates, then whoever administers the wind-down: an assignee for the benefit of creditors or a bankruptcy trustee. They act for the company and its creditors, and Origin pays them nothing.

### What does Origin charge a design firm?

Nothing. Origin does not charge data owners; a buyer may pay Origin when a deal closes. You approve every step and sign the license yourself.

## Sources

- [Anthropic: Research Engineer, Chip Design RL (job post)](https://job-boards.greenhouse.io/anthropic/jobs/5459098008)
- [OpenAI: Research Engineer, AI for Chip Design (job post)](https://openai.com/careers/research-engineer-ai-for-chip-design-san-francisco/)
- [Prime Intellect: Applied Researcher, Chip Design (job post)](https://jobs.ashbyhq.com/PrimeIntellect/9ed2340b-029e-4f58-82f5-0d55f09aad5b)
- [Phinity Labs: Research Engineer, Hardware Data (job post)](https://jobs.ashbyhq.com/Phinitylabs/510b00e6-c8d3-42ae-8c28-81e91672aef8)
- [Mercor: Chip Design Expert (RTL Design and Verification) listing](https://work.mercor.com/jobs/list_AAABoc1YpFIYUktJmyxFc5mB/chip-design-expert-rtl-design-verification)
- [SemiAnalysis: GDPx, measuring frontier model capabilities (2 November 2026)](https://newsletter.semianalysis.com/p/gdpx-measuring-frontier-model-capabilities)
- [Phoenix-bench (arXiv 2605.15226): agentic AI on hardware repositories](https://arxiv.org/abs/2605.15226)
- [15 CFR 730.3: "dual use" and other items subject to the EAR](https://www.law.cornell.edu/cfr/text/15/730.3)
- [15 CFR 734.3: items subject to the EAR, including EAR99](https://www.law.cornell.edu/cfr/text/15/734.3)
- [15 CFR 734.13: export, including deemed export](https://www.law.cornell.edu/cfr/text/15/734.13)
- [15 CFR part 774, supplement 1: Commerce Control List, Category 3 (3E001, 3E905, 3E991 and the PDK note)](https://www.ecfr.gov/current/title-15/subtitle-B/chapter-VII/subchapter-C/part-774/appendix-Supplement%20No.%201%20to%20Part%20774)
- [Federal Register, 13 October 2022: BIS rule on advanced computing and semiconductor manufacturing items](https://www.federalregister.gov/documents/2022/10/13/2022-21658/implementation-of-additional-export-controls-certain-advanced-computing-and-semiconductor-manufacturing)
- [SkyWater Open Source PDK (Google and SkyWater, Apache 2.0)](https://github.com/google/skywater-pdk)
- [GF180MCU open PDK (GlobalFoundries, Apache 2.0)](https://github.com/google/gf180mcu-pdk)

## Related reading

- [License Semiconductor Process and Design Data for AI](https://origindatapartners.com/guides/license-semiconductor-process-data-ai)
- [ITAR and EAR Checklist Before You Share CAD Files With AI](https://origindatapartners.com/guides/itar-ear-checklist-cad-data-ai)
- [Gerber Files and PCB Design Data: What Altium and KiCad Hold](https://origindatapartners.com/guides/altium-kicad-pcb-design-data-ai)
- [Hardware Startup Shutdown: What Happens to the CAD Archive](https://origindatapartners.com/guides/hardware-company-closing-cad-archive)
- [Tapeout: What It Means, Plus a Tapeout Checklist (CSV)](https://origindatapartners.com/guides/tapeout-checklist)
- [UVM Testbench: Architecture, Components and an Example](https://origindatapartners.com/guides/uvm-testbench-example)
- [Design Verification Plan Template: Coverage and Sign-off](https://origindatapartners.com/guides/design-verification-plan-template)
- [/glossary/process-design-kit](https://origindatapartners.com/glossary/process-design-kit)
- [/glossary/uvm](https://origindatapartners.com/glossary/uvm)
- [Agent Traces: Licensing Production AI Agent Runs (2026)](https://origindatapartners.com/guides/license-ai-agent-traces)